1. Field of the Invention
This invention relates to a display apparatus, especially to a driving circuit applied to a LCD apparatus.
2. Description of the Prior Art
Please refer to FIG. 1. FIG. 1 illustrates a schematic diagram of the conventional driving circuit applied to the LCD apparatus. As shown in FIG. 1, the driving circuit 1 includes a first channel CH1 and a second channel CH2. Wherein, the first channel CH1 includes latching units 10A and 11A, a level shifting unit 12A, a digital-analog converting unit 13A and an operational amplifying unit 14A; the second channel CH2 includes latching units 10B and 11B, a level shifting unit 12B, a digital-analog converting unit 13B and an operational amplifying unit 14B. The input terminals of the latching units 10A and 10B are coupled to two output terminals of the shifting register SR respectively.
The transistor SW1 is coupled between the output terminal of the operational amplifying unit 14A and a positive voltage (3V). The gate of the transistor SW1 is coupled to the switches PSW1 and PSW2 respectively, wherein the switch PSW1 is coupled to another positive voltage (6V) and the switch PSW2 is coupled between the digital-analog converting unit 13A and the operational amplifying unit 14A. When the digital-analog converting unit 13A inputs an input voltage higher than the positive voltage 3V into the operational amplifying unit 14A, the switch PSW1 will be switched on and the switch PSW2 will be switched off. Otherwise, the switch PSW2 will be switched on and the switch PSW1 will be switched off.
Similarly, the transistor SW2 is coupled between the output terminal of the operational amplifying unit 14B and a negative voltage (−3V). The gate of the transistor SW2 is coupled to the switches PSW3 and PSW4 respectively, wherein the switch PSW3 is coupled to another negative voltage (−6V) and the switch PSW4 is coupled between the digital-analog converting unit 13B and the operational amplifying unit 14B. When the digital-analog converting unit 13B inputs an input voltage higher than the positive voltage 3V into the operational amplifying unit 14B, the switch PSW3 will be switched on and the switch PSW4 will be switched off. Otherwise, the switch PSW4 will be switched on and the switch PSW3 will be switched off.
Compared with the ordinary amplifier OP driving data by driving the voltage source having AVDD level or NAVDD level all the time to charge to a target voltage level, the power saving mechanism of this driving circuit structure is to drive the voltage source having VCI level or NVCI level to pre-charge to a specific voltage level at first and then drive the voltage source having AVDD level or NAVDD level to continuously charge to the target voltage level.
By doing so, if AVDD=2*VCI and NAVDD=2*NVCI, there will be about half of the power consumption can be saved before driving the voltage source having AVDD level or NAVDD level to charge.
However, the above-mentioned driving circuit structure has the following drawbacks:
(1) When the value of the data becomes zero, the charges stored in the data line capacitor will not be collected.
(2) Using the most significant bit (MSB) of the data and pre-charging to the VCI level or NVCI level may cause over-charging and more power consumption.